In JP-A No. 039872/1999, there has been proposed a dynamic RAM which aims at rapid processing by increasing a voltage applied between a source and a drain of a differential MOSFET which precharges bit lines with a ground potential VSS of a circuit and constitutes a sense amplifier. In this publication, a capacitance value of capacitors of dummy cells is set to a half of a capacitance value of capacitors of normal memory cells thus forming a reference voltage supplied to the bit lines.
In such a dynamic RAM adopting the above-mentioned VSS precharge method, it is difficult to form the capacitance value of the dummy cell capacitors at ½ of a capacitance value of capacitors of the normal memory cells. Hence, there arises a drawback that a signal quantity difference is decreased due to process irregularities and a read margin of the sense amplifier is decreased. Further, it is also found that when a circuit having a different pattern than a pattern of the memory array is formed in a periphery of the memory array, the formability of a normal portion is deteriorated due to the coarseness and denseness of a layout pattern. The signal margin is also deteriorated.
In FIG. 1 and FIG. 2, a schematic circuit diagram of a dynamic RAM (hereinafter, simply referred to as a DRAM) which was studied in the course of arriving at the present invention is shown. FIG. 1 shows the DRAM adopting a VDD/2 precharge method and FIG. 2 shows the DRAM adopting a VSS precharge method as discussed in the above-mentioned publication. Although there is no specific limitation, the DRAMs shown in FIG. 1 and FIG. 2 adopt a fold-back bit line method (or a two crossing points method) in which a pair of complementary bit lines BLT, BLB extend in parallel with respect to a sense amplifier (V and SA, respectively). The DRAMS also adopt a shared sense amplifying method in which the sense amplifier is arranged between the above-mentioned pair of bit lines while the bit lines are respectively arranged on either side of the sense amplifier. In these drawings, the pair of bit lines BLT, BLB is illustrated as a representative example.
In FIG. 1 and FIG. 2, a precharge circuit is constituted of a MOSFETQ1 which is provided to input/output nodes of the sense amplifier SA and short-circuits the complementary bit lines BLT, BLB which are connected to each other by way of shared switches MOSFETQ4 and MOSFETQ5 (as illustrated in FIG. 1), and MOSFETQ2 and MOSFETQ3 which supply a precharge voltage based on the precharge activating signal to the bit lines BLT, BLB. In the VDD/2 precharge circuit, the precharge voltage VDD/2 is supplied through the above-mentioned MOSFETQ2 and MOSFETQ3. On the other hand, in the VSS precharge circuit shown in FIG. 2, the precharge voltage VSS is supplied through the above-mentioned MOSFETQ2 and MOSFETQ3. During a precharge period in which MOSFETQ1 and MOSFETQ3 assume an ON state, the above-mentioned shared switches MOSFETQ4 and MOSFETQ5 assume an ON state. Also with respect to the complementary bit lines at another side not shown in the drawing, the complementary bit lines are provided by way of a shared switch MOSFET having the substantially same constitution.
In the VDD/2 precharge method shown in FIG. 1, the bit lines BLT and BLB are normally held at a VDD/2 level during the precharge period. When a word line WL rises, information corresponding to a “0”/“1” stored in the memory cell is read to the bit line BLT as a minute signal quantity difference of +/−ΔVBL with respect to VDD/2 which constitutes the center of the voltage range. Thereafter, when the sense amplifier SA commences operation, the signal quantity difference is compared with a potential of the bit line BLB and a “H”/“L” is judged using the VDD/2 level of the bit line BLB as the reference (the reference voltage).
On the other hand, in the VSS precharge method shown in FIG. 2, which includes gate line PE2, dummy word line DWL and VII, the bit lines are normally discharged to assume a VSS level during the precharge period. When the word line WL rises, although a normal memory cell charge is read to the bit line BLT, a bit line potential is not changed in case of “0” data. Accordingly, the potential (reference voltage) of the bit line BLB which is compared at the time of differential amplifying is required to assume an intermediate value which can obtain a minute read voltage +/−ΔVBL corresponding to a binary value voltage which corresponds to the normal memory cell data of a “0”/“1”.
In the above-mentioned patent application, the reference potential (reference voltage) is generated using dummy cells having a capacitance which is half of the capacitance of the normal memory cells. In the VSS precharge method, compared to the VDD/2 method, the extra number of elements becomes necessary by an amount corresponding to the dummy cells and a dummy cell control circuit and hence, it is difficult to make a layout which can constitute the circuit while suppressing an increase in area. Further, since a charge and a discharge of the bit line capacitance are conducted for every read cycle, compared to the VDD/2 precharge method which generates the precharge potential by redistributing the charge, power consumption is increased.
In view of the above, the conventional general-use DRAMS or the like have adopted the VDD/2 precharge method. However, recently, when the bit line voltage VDD, that is, an operational voltage of a sense amplifier is lowered along with miniaturization of the DRAMS, a drawback in terms of amplifying speed delay is expected to arise. This is because a source-drain voltage which is applied to both ends of the center amplifier becomes small at the time of amplifying. In the future, when the above-mentioned voltage VDD becomes 1.0 V or less, it is expected that a considerable time will be required for amplifying the initial minute signal difference +/−ΔVBL which is read to the bit lines. To overcome this drawback, the inventors of the present invention have restudied the VSS precharge method to obtain a source-drain voltage twice as large as the source-drain voltage of the VDD/2 precharge method.
To realize the above-mentioned VSS precharge method, it is necessary to construct a circuit such that half of the normal memory cell charge is charged in the dummy cells. A VSS precharge circuit utilizes a Cs/2 memory cell to realize a method in which a capacitance value of the dummy cell is set to Cs/2, which is half of the normal memory cell potential and a charge of Cs×VDD/2 is stored in the dummy cells by charging with the bit line voltage VDD. In this method, it is difficult to form the dummy cells having a capacitance which is half of the memory cells and hence, there arises a drawback in that the read margin is lowered when a process becomes irregular. Further, it has been also found that when the circuit having a pattern different from the memory array is provided in a periphery of the memory array as mentioned above, the formability of the normal portion is deteriorated due to the coarseness and the fineness of the layout pattern and hence, the signal margin is further deteriorated.
Accordingly, the inventors of the present invention have considered a usual memory-cell-use type VSS precharge circuit, that is, a method which sets the dummy cell capacitance to Cs which is equal to the capacitance of the normal memory cell and performs charging using the VDD/2 level voltage. By adopting this method, as the dummy cells, it is possible to use the memory cell which is equal to the memory cell used as the normal memory cells and hence, the dummy cells can be formed by a substantially equal fabrication process. At the same time, the degree of irregularities becomes substantially equal between the normal memory cells and the dummy cells. Thereby, the fabrication margin is enhanced. However, to supply the charge of Cs×VDD/2 to the dummy cells, it is necessary either to charge VDD/2 to the inside of the dummy cells through the bit lines BLB, BLT, or to add a special circuit for charging the dummy cells. When the charging is performed through the bit lines, a resistance value is large and hence, a charging time is increased and the merit of adopting the VSS precharge method is decreased. Hence, it is necessary to construct a circuit such that the charge is directly supplied to storage nodes of the capacitors of the dummy cells.
To add such a circuit, it is necessary to layout the dummy cells apart from the memory array having a narrow pitch and hence, a peripheral pattern becomes coarse whereby there exists a possibility that cell shape is changed. In this manner, it has been found that, in such a memory array, the formability of the normal portion is deteriorated due to the coarseness and fineness of the layout pattern and the construction which makes the degree of irregularities substantially equal between normal cells and the dummy cells is not utilized and the signal margin is further deteriorated. That is, the reduction of the forming irregularities which is the advantageous effect obtained by making the capacitance of the dummy cells to Cs which is also the capacitance of the normal memory cells is lost. Hence, eventually, there arises the displacement in the reference potential attributed to the charge supplied to the dummy cells whereby the read margin at the time of performing the sensing operation is decreased.